Vlsi HEADSPEAKER - 5.1 Spezifikationen PDF herunterladen (Seite 23)

VLSI

Solution

VS1053b

VS1053B

7. SPI BUSES

7.6 SPI Timing Diagram

XCS

SCK

0 1 1514 16

tXCSS

tXCSH

tWL tWH

tSU

tDIS

tXCS

Figure 9: SPI Timing Diagram.

Symbol Min Max Unit

tXCSS 5 ns

tSU 0 ns

tH 2 CLKI cycles

tZ 0 ns

tWL 2 CLKI cycles

tWH 2 CLKI cycles

tV 2 (+ 25 ns

) CLKI cycles

tXCSH 1 CLKI cycles

tXCS 2 CLKI cycles

tDIS 10 ns

25 ns is when pin loaded with 100 pF capacitance. The time is shorter with lower capacitance.

Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0×

mode, thus CLKI=XTALI. After you have conﬁgured a higher clock through SCI CLOCKF and waited

for DREQ to rise, you can use a higher SPI speed as well.

Note: Because tWL + tWH + tH is 6×CLKI + 25 ns, the maximum speed for SCI reads is CLKI/7.

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